A DLL (Delay Locked Loop) circuit includes a delay circuit whose delay time can be variably controlled, a phase detector that compares an output of the delay circuit and an input signal supplied to the delay circuit, and a counter that counts up or down based on a result of phase comparison by the phase detector. The delay time by the delay circuit is adjusted to pull the output of the delay circuit into synchronization with the input signal to the delay circuit, based on a count value or on the result of decoding by the counter. As such a DLL circuit, there is known a configuration including a variable delay circuit and a synthesizing circuit, also termed an interpolation circuit or an interpolator. The variable delay circuit effects coarse delay adjustment and the interpolation circuit effects fine delay adjustment. Specifically, the variable delay circuit sets the delay time with a coarser delay resolution (delay time unit) and the synthesizing circuit synthesizes the phase difference (delay) between two signals with different delay time values, generated by the variable delay circuit, in accordance with a preset synthesis ratio, thereby generating a delay signal higher in resolution than the delay time unit of the variable delay circuit. The synthesizing circuit (interpolator) performs internal division of the delays of the two signals to output a signal of intermediate delay, and includes a precharging circuit and first and second discharge elements. The precharging circuit precharges a preset node beforehand to a prescribed voltage. The first and second discharge elements are turned on (i.e., made conductive) during a HIGH period of first and second input signals to discharge the precharged node to current values of XI and (1−X)I related with an internal division ratio X:(1−X), where 0≦X≦1. As regards the detailed configuration of the synthesizing circuit (interpolator) that synthesizes the two signals (Even and Odd) of different delay time values from the variable delay circuit, as well as the detailed configuration of the DLL circuit, see Patent Document 1, for instance.
Recently, operating frequencies of semiconductor circuits have increased significantly. Hence, in a DLL circuit that controls the delay of a high speed clock, duty offset, for example, is becoming a significant problem. Patent Document 2 has disclosed a digital DLL circuit capable of separately controlling delays on rising and falling of a signal and also capable of compensating for a clock duty offset or the rise/fall delay difference of a data signal. The circuit configuration of the DLL circuit disclosed is such that a variable delay circuit (D0_R variable delay circuit) delays an input signal (data) with a delay corresponding to a rising delay control value provided by a control circuit. A one-shot pulse is generated from a delayed output of the variable delay circuit and supplied to a set terminal of an SR flip-flop. A variable delay circuit (D0_F variable delay circuit) delays an input signal (data) with a delay corresponding to the fall delay control value supplied by the control circuit. A one-shot pulse is generated from a delayed output of the variable delay circuit and supplied to a reset terminal of an SR flip-flop. A delayed output is derived from an output of the SR flip-flop.
Patent Document 3 discloses a configuration of a semiconductor integrated circuit device for generating a clock, whose delay time and duty ratio may be made selectable, without causing jitter deterioration. With this configuration, two clocks from the DLL circuit are used to determine the rising and falling edges of a generated clock. The delay time of the two clocks from the DLL circuit are made selectable. The two clocks selected are supplied to two inputs of the clock synthesis circuit including D-flip-flops that receives two inputs. The timing of the rising and falling edges of the output clock is determined by the rising edges of the two input clocks based on the function of a phase frequency comparator. Thus, by optionally selecting the phase (delay time) of the two input clocks, an output clock is derived that has a desired duty ratio and a desired delay time value.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2003-91331A, corresponding to US 2003/052718, now U.S. Pat. No. 6,674,314 (FIGS. 1 and 3)
[Patent Document 2] JP Patent Kokai Publication No. JP-P2007-228044A, corresponding to US 2007/194824 (FIG. 4)
[Patent Document 3] JP Patent Kokai Publication No. JP-P2008-136031A (FIG. 2)
The entire disclosures of Patent Documents 1 to 3 are incorporated herein by reference thereto.